This document describes the procedure of applying EGG framework to combinational logic circuit synthesis as an example. You can get the source files of the example in egg/examples/01-combinational.
- Type of nodes for representing circuit graphs
Consider design problem of combinational logic circuits using the following logic gates (nodes):
- 2-input 1-output AND gate
- 2-input 1-output XOR gate
- 3-input 1-output AND gate
- 3-input 1-output XOR gate
- Constant 1
- Evaluation function of the circuit graphs
The circuit graphs are evaluated by a combination of two different evaluation functions, functionality F and performance P. The functionality measure F evaluates the validity of the logical function compared with the target function. The performance measure P, on the other hand, is assumed to be the product of circuit delay D and the area A.
- Functionality measure F
Calculate first the following quantities x, which estimate the distance between the target function and the function obtained from the circuit graph. Then determine the Fitness value F
F = 100(1-x/(m2n)),
where n is the number of inputs and m is the number of outputs, respectively. - Performance measure P
Calculate the following equation:
P = C/(DA).
The constant C adjusts the ratio P/F to about 5/100.
Step 1: Create initial files for developing the application.
Execute generate.pl and make EGCControl.h, EGCEvaluation.cpp/h, EGCFitness.h, EGCGraph.h, EGCNode.cpp/h, EGCSubGraph.h, EGCTerminal.h, Makefile.am, and main.cpp.
Step 2: Determine the type of nodes.
- EGCNode class inherits from EGTNode.
- Enumerate the type of nodes.
- enum node_t { OUTPUT, INPUT, AND, XOR, AND3, XOR3, VIN, C1 }
- Override the following pure virtual functions for creating the nodes.
- Override the following virtual function for the evolutionary operations.
- Override the following virtual function for generating log files
Step 3: Give functions for reducing the search space.
If a target circuit to be synthesized belongs to a specific type of circuit graphs which are characterized by some graph theoretic constraints, we can reduce the search space by using the constraints.
In this example, a combinational logic circuit is modeled as Complete Circuit Forest (CCF), which is a kind of complete circuit graphs without any feedback loops. Therefore, we can reduce the search space by the constraint of CCF. The EGG system is designed to consider only CCFs in the evolution process by using the following derived classes.
- EGCSubGraph class inherits from EGTSubGraph.
- Override the following members for generating circuit graphs (or sub-circuit graphs) as CCFs.
- EGCGraph class inherits from EGTGraph.
- Define the following member for checking whether the newly generated circuit graph is CCF or not.
- IsCompleteCircuitForest()
Step 4: Determine the evaluation function.
- EGCControl class inherits from EGTControl.
- Override the following pure virtual function for loading the target functionality.
The target functionality is given by a "target.dat" file in the following file format.
<NUM_INPUTS> <NUM_OUTPUTS>
<INPUT_0> <INPUT_1> ... <INPUT_N> <OUTPUT_0> <OUTPUT_1> ... <OUTPUT_M>
<INPUT_0> <INPUT_1> ... <INPUT_N> <OUTPUT_0> <OUTPUT_1> ... <OUTPUT_M>
<INPUT_0> <INPUT_1> ... <INPUT_N> <OUTPUT_0> <OUTPUT_1> ... <OUTPUT_M>
...
Ex. 3-input 2-output full adder (in_0 + in_1 + in_2 = out_0 + 2 * out_1) 3 2
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
- EGCEvaluation class inherits from EGTEvaluation.
- Override the following pure virtual function for determining the fitness value of individuals.
- Define the following members used in the evaluation of the circuit graph.
- tInputVec
- tOutputVec
- UpdateValue()
- EvaluateFunctionality()
- EvaluatePerformance()
- EvaluateCorrelation()
- EvaluateDelay()
- EvaluateArea()
- EGCNode class inherits from EGTNode.
- Define the following members used in the evaluation of the circuit graph.
- m_eState
- GetState()
- SetState()
- ClearValue()
- UpdateOutput()
- GetArea()
- GetDelay()
- EGCFitness class inherits from EGFitness.
- Override the pure virtual function for getting the fitness value of individuals.
- Overload operator== and operator!=.
- Define the following members for getting the fitness values.
- GetFunctionality()
- GetPerformance()
- Define the display method in Display().
- EGCTerminal class inherits from EGTTerminal.
- Overload the following member function.
- Define the following members used in the evaluation of the circuit graph.
- m_uValue
- GetValue()
- SetValue()