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Example application: Synthesis of combinational logic circuits

This document describes the procedure of applying EGG framework to combinational logic circuit synthesis as an example. You can get the source files of the example in egg/examples/01-combinational.


Determine the design specification.


Derive new classes from the class templates.

Step 1: Create initial files for developing the application.

Execute generate.pl and make EGCControl.h, EGCEvaluation.cpp/h, EGCFitness.h, EGCGraph.h, EGCNode.cpp/h, EGCSubGraph.h, EGCTerminal.h, Makefile.am, and main.cpp.

Step 2: Determine the type of nodes.

Step 3: Give functions for reducing the search space.

If a target circuit to be synthesized belongs to a specific type of circuit graphs which are characterized by some graph theoretic constraints, we can reduce the search space by using the constraints.

In this example, a combinational logic circuit is modeled as Complete Circuit Forest (CCF), which is a kind of complete circuit graphs without any feedback loops. Therefore, we can reduce the search space by the constraint of CCF. The EGG system is designed to consider only CCFs in the evolution process by using the following derived classes.

Step 4: Determine the evaluation function.