Introduction
This project is one of the research activities
in Aoki laboratory, Tohoku University.
We are conducting research to
develop advanced cryptographic hardware
and to investigate their vulnerability
against side-channel attacks.
Contents
- Home
- Academic Publications (International), Academic Publications (Domesitic)
- IP Cores
- Side-channel Attack Standard Evaluation Board (SASEBO)
This page.
List of our academic publications and their PDFs.
Distributing HDL code of some ciphers.
Informations for an FPGA board specialized for side-channel attack experiments.
Update history
- 2009/SEP/15
- 2008/OCT/02
- 2008/AUG/20
- 2008/JUN/02
- 2008/APR/07
- 2008/JAN/25
- 2008/JAN/12
- 2007/DEC/17
- 2007/NOV/28
- 2007/OCT/04
- 2007/SEP/25
- 2007/SEP/19
- 2007/SEP/07
- 2007/AUG/07
Academic publications are updated.
Academic publications are updated.
Academic publications are updated.
Academic publications are updated.
A code for RSA processor with the Montgomery multiplier is added to IP Cores.
Academic publications are updated.
SASEBO-AES.zip is fixed.
Web page on Side-channel Attack Standard Evaluation Board (SASEBO) is uploaded.
Academic Publications is updated.
Fixes in AES_Comp.v and CAST128.v
HDL codes and specification documents are updated in IP Cores.
AES2.v, AES_TB2.v are updated.
A new specification document (AESSpec2007Sep14.pdf)
is added to IP Cores.
New codes (TDEA.v, TDEA_tb.v) are added to IP Cores.
New specification documents (DESSpec2007Sep05.pdf,
TDEASpec2007Sep05.pdf) are added to IP Cores.
Some codes (DES_ECB.v, DES_TB.v) are updated.
Academic Publications is updated.
New codes (AES2.v, AES_TB2.v, JWIS2007.zip) are added to IP Cores.
Academic Publications is updated.
