Introduction

This project is one of the research activities in Aoki laboratory, Tohoku University.
We are conducting research to develop advanced cryptographic hardware and to investigate their vulnerability against side-channel attacks.

Contents

• Home

This page.

• Academic Publications (International), Academic Publications (Domesitic)

List of our academic publications and their PDFs.

• IP Cores

Distributing HDL code of some ciphers.

• Side-channel Attack Standard Evaluation Board (SASEBO)

Informations for an FPGA board specialized for side-channel attack experiments.

Contact information

TEL: +81-22-795-7169
FAX: +81-22-263-9308
E-mail:cryptaoki.ecei.tohoku.ac.jp

Update history

• 2012/MAY/9

On-chip glitchy-clock generator is added to IP cores .

• 2011/OCT/17

glitchy-clock_generator.zip is added.

• 2009/SEP/15

Academic publications are updated.

• 2008/OCT/02

Academic publications are updated.

• 2008/AUG/20

Academic publications are updated.

• 2008/JUN/02

Academic publications are updated.

• 2008/APR/07

A code for RSA processor with the Montgomery multiplier is added to IP Cores.

• 2008/JAN/25

Academic publications are updated.

• 2008/JAN/12

SASEBO-AES.zip is fixed.

• 2007/DEC/17

Web page on Side-channel Attack Standard Evaluation Board (SASEBO) is uploaded.

• 2007/NOV/28

Academic Publications is updated.

• 2007/OCT/04

Fixes in AES_Comp.v and CAST128.v

• 2007/SEP/25

HDL codes and specification documents are updated in IP Cores.

• 2007/SEP/19

AES2.v, AES_TB2.v are updated. A new specification document (AESSpec2007Sep14.pdf) is added to IP Cores.

• 2007/SEP/07

New codes (TDEA.v, TDEA_tb.v) are added to IP Cores. New specification documents (DESSpec2007Sep05.pdf, TDEASpec2007Sep05.pdf) are added to IP Cores. Some codes (DES_ECB.v, DES_TB.v) are updated. Academic Publications is updated.

• 2007/AUG/07

New codes (AES2.v, AES_TB2.v, JWIS2007.zip) are added to IP Cores. Academic Publications is updated.