Hardware algorithms for arithmetic modules

Arithmetic Module Generator (AMG) supports various hardware algorithms for two-operand adders and multi-operand adders. These hardware algorithms are also used to generate multipliers, constant-coefficient multipliers and multiply accumulators. In the following, we briefly describe the hardware algorithms that can be handled by AMG.

Two-operand adders

Ripple carry adder (RCA)

The most straightforward implementation of a final stage adder for two n-bit operands is a ripple carry adder, which requires n full adders (FAs). The carry-out of the ith FA is connected to the carry-in of the (i+1)th FA. Figure 1 shows a ripple carry adder for n-bit operands, producing n-bit sum outputs and a carry out.

n-bit ripple carry adder
Figure 1. n-bit ripple carry adder

Carry look-ahead adder (CLA)

The main idea behind carry look-ahead addition is an attempt to generate all incoming carries in parallel and avoid waiting until the correct carry propagates from the stage (FA) of the adder where it has been generated.
The carry, Ci+1, produced at the ith stage is given as follows:


The equation can be interpreted as stating that there is a carry either if one is generated at that stage or if one is propagated from the preceding stage. In other words, a carry is generated if both operand bits are 1, and an incoming carry is propagated if one of the operand bits is 1 and the other is 0. Therefore, let Gi and Pi denote the generation and propagation at the ith stage, we have:

 G, P, c

for operand bit xi and yi and carry-in ci. These expressions allow us to calculate all the carries in parallel from the operands. For example, the carries for a 4-bit adder are given as


A 4-bit carry look-ahead adder is designed so as to realize the above expressions.

Ripple-block carry look-ahead adder (RCLA)

The idea of the ripple-block carry look-ahead addition is to lessen the fan-in and fan-out difficulties inherent in carry look-ahead adders. A ripple-block carry look-ahead adder (RCLA) consists of N m-bit blocks arranged in such a way that carries within blocks are generated by carry look-ahead but carries between blocks are rippled.

The block size m is fixed to 4 in the generator. The RCLA design is obtained by using multiple levels of carry look-ahead. If there are five or more blocks in a RCLA, 4 blocks are grouped into a single superblock, with the second level of look-ahead applied to the superblocks.

Figure 2 shows the parallel prefix graph of a 64-bit RCLA, where the symbol (solid circle) indicates an extension of the fundamental carry operator described at Parallel prefix adders.

64-bit ripple-block carry look-ahead adder
Figure 2. 64-bit ripple-block carry look-ahead adder

Block carry look-ahead adder (BCLA)

Another way to design a practical carry look-ahead adder is to reverse the basic design principle of the RCLA, that is, to ripple carries within blocks but to generate carries between blocks by look-ahead. A block carry look-ahead adder (BCLA) is based on the above idea.

Figure 3 shows the parallel prefix graph of a 64-bit BCLA, where the symbol (solid circle) indicates an extension of the fundamental carry operator described at Parallel prefix adders.

64-bit Block carry look-ahead adder
Figure 3. 64-bit Block carry look-ahead adder

Parallel prefix adders (Ladner-Fischer adder, Kogge-Stone adder, Brent-Kung adder, Han-Carlson adder)

Parallel prefix adders are constructed out of fundamental carry operators denoted by ¢ as follows:
 (G'', P'') ¢ (G', P') = (G''+G'·P'', P'·P''),
where P'' and P' indicate the propagations, G'' and G' indicate the generations. The fundamental carry operator is represented as Figure 4.

Carry operator
Figure 4. Carry operator

A parallel prefix adder can be represented as a parallel prefix graph consisting of carry operator nodes.

Figure 5 is the parallel prefix graph of a Ladner-Fischer adder. This adder structure has minimum logic depth, but has large fan-out requirement up to n/2.

Ladner-Fischer adder
Figure 5. 16-bit Ladner-Fischer adder

Figure 6 is the parallel prefix graph of a Kogge-Stone adder. This adder structure has minimum logic depth, and full binary tree with minimum fun-out, resulting in a fast adder but with a large area.

Kogge-Stone adder
Figure 6. 16-bit Kogge-Stone adder

Figure 7 is the parallel prefix graph of a Brent-Kung adder. This adder is the extreme case of maximum logic depth and minimum area.

Brent-Kung adder
Figure 7. 16-bit Brent-Kung adder

Figure 8 is the parallel prefix graph of a Han-Carlson adder. This adder has a hybrid design combining stages from the Brent-Kung and Kogge-Stone adder.

Han-Carlson adder
Figure 8. 16-bit Han-Carlson adder

Conditional sum adder

The basic idea in the conditional sum adder is to generate two sets of outputs for a given group of operand bits, say, k bits. Each set includes k sum bits and an outgoing carry. One set assumes that the eventual incoming carry will be zero, while the other assumes that it will be one. Once the incoming carry is known, we need only to select the correct set of outputs (out of the two sets) without waiting for the carry to further propagate through the k positions.

In this generator, we divide the given n-bit operands into two groups of size n/2 bits each. Each of these can be further divided into two groups of n/4 bits each. This process can, in principle, be continued until a group of size 1 is reached. The above idea is applied to each of groups separately.

Figure 9 depicts a conditional sum adder for 4-bit operands.

Conditional sum adder
Figure 9. 4-bit conditional sum adder

Carry select adder

The underlying strategy of the carry-select adder is similar to that of the conditional-sum adder. Each group generates two sets of sum bits and an outgoing carry. One set assumes that the incoming carry into the group is 0, the other assumes that it is 1. When the incoming carry into the group is assigned, its final value is selected out of the two sets. Unlike the conditional-sum adder, the sizes of the kth group is chosen so as to equalize the delay of the ripple-carry within the group and the delay of the carry-select chain from group 1 to group k. In this generator, the group lengths follow the simple arithmetic progression 1, 1, 2, 3, ...

Figure 10 shows a 16-bit carry select adder.

Carry select adder
Figure 10. 16-bit carry select adder

Carry-skip adder
(Fixed-block-size carry-skip adder, Variable-block-size carry-skip adder)

A carry-skip adder reduces the carry-propagation time by skipping over groups of consecutive adder stages. The carry-skip adder is usually comparable in speed to the carry look-ahead technique, but it requires less chip area and consumes less power.

In the carry-skip adder, any adder stage can be skipped for which Pm = xm exor ym = 1, where Pm indicates the m th carry propagate. The adder structure is divided into blocks of consecutive stages with a simple ripple-carry scheme. Every block also generates a block-carry-propagate signal that equals 1 if all stages internal to the block satisfy Pm = 1. This signal can be used to allow an incoming carry to skip all the stages within the block and generate a block-carry-out. Figure 11 shows an example block consisting of k bit positions j, j+1, ..., j+k-1.

Carry skip block
Figure 11. carry-skip block.

Figure 12 shows an 8-bit carry-skip adder consisting of four fixed-size blocks, each of size 2. The fixed block size should be selected so that the time for the longest carry-propagation chain can be minimized.
The optimal block size k_opt follows:  kopt.

carry-skip adder
Figure 12. 8-bit Fixed-block-size carry-skip adder.

Figure 13 shows a 16-bit carry-skip adder consisting of seven variable-size blocks. This optimal organization of block size includes L blocks with sizes k1, k2, ..., kL = 1, 2, 3, ..., 3, 2, 1. This reduces the ripple-carry delay through these blocks.

Variable-block-size carry-skip
Figure 13. 16-bit Variable-block-size carry-skip adder.

Please note that the delay information of carry-skip adders in Reference data page is simply estimated by using false paths instead of true paths.
Figure 14 compares the delay information of true paths and that of false paths in the case of Hitachi 0.18 um process.

Figure 14. delay.

Multi-operand adders (in carry-save form)

Table 1 shows hardware algorithms that can be selected for multi-operand adders in AMG, where the bit-level optimized design indicates that the matrix of partial product bits is reorganized to optimize the number of basic components.

Table 1. Hardware Algorithms for Multi-operand adder
Classfication of Multi-operand adders


Array is a straightforward way to accumulate partial products using a number of adders.
The n-operand array consists of n-2 carry-save adder. Figure 15 shows an array for 18-operand, producing 2 outputs, where CSA indicates a carry-save adder having three multi-bit inputs and two multi-bit outputs.

Figure 15. Array

Wallace tree

Wallace tree is known for their optimal computation time, when adding multiple operands to two outputs using carry-save adders. The Wallace tree guarantees the lowest overall delay but requires the largest number of wiring tracks (vertical feedthroughs between adjacent bit-slices). The number of wiring tracks is a measure of wiring complexity. Figure 16 shows an 18-operand Wallace tree, where CSA indicates a carry-save adder having three multi-bit inputs and two multi-bit outputs.

Wallace tree
Figure 16. Wallace tree

Balanced delay tree

Balanced delay tree requires the smallest number of wiring tracks but has the highest overall delay compared with the Wallace tree and the overturned-stairs tree.
Figure 17 shows an 18-operand balanced delay tree, where CSA indicates a carry-save adder having three multi-bit inputs and two multi-bit outputs.

Balanced delay tree
Figure 17. Balanced delay tree

Overturned-stairs tree

Overturned-stairs tree requires smaller number of wiring tracks compared with the Wallace tree and has lower overall delay compared with the balanced delay tree.
Figure 18 shows an 18-operand overturned-stairs tree, where CSA indicates a carry-save adder having three multi-bit inputs and two multi-bit outputs.

Overturned-stairs tree
Figure 18. Overturned-stairs tree

(4;2) compressor tree

(4;2) compressor tree has a more regular structure than an ordinary CSA tree made of (3,2) counters because the partial products are added up in the form of a binary tree.
Figure 19 shows an 18-operand (4;2) compressor tree, where (4;2) indicates a carry-save adder having four multi-bit inputs and two multi-bit outputs.

(4;2) compressor tree
Figure 19. (4;2) compressor tree

Dadda tree

Dadda tree is based on (3,2) counters. To reduce the hardware complexity, we allow the use of (2,2) counters in addition to (3,2) counters. Given the matrix of partial product bits, the number of bits in each column is reduced to minimize the number of (3,2) and (2,2) counters.

(7,3) counter tree

A (7,3) counter tree is based on (7,3) counters. To reduce the hardware complexity, we allow the use of (6,3), (5,3), (4,3), (3,2), and (2,2) counters in addition to (7,3) counters. We employ Dadda's strategy for constructing (7,3) counter trees.

Redundant binary addition tree

Redundant binary (RB) addition tree has a more regular structure than an ordinary CSA tree made of (3,2) counters because the RB partial products are added up in the binary tree form by RB adders. The RB addition tree is closely related to (4;2) compressor tree. Figure 20 shows a 9-operand RB addition tree, where RB indicates a carry-save adder having two RB inputs and one RB output. Note here that the RB number should be encoded into a vector of binary digit in the standard binary-logic implementation. In this generator, we employ a minimum length encoding based on positive-negative representation.

Redundant binary addition tree
Figure 20. Redundant binary addition tree

Partial product generators (PPG)

Simple PPG (without Radix-4 modified Booth recoding)

Partial products result from the logical AND of the multiplicand with the multiplier.

PPG with Radix-4 modified Booth recoding

Partial products are generated with Radix-4 modified Booth recoding. The Booth recoding of the multiplier reduces the number of partial products (and hence has a possibility of reducing the amount of hardware involved and the execution time).


AMG provides parallel multipliers consisting of Partial Product Generator (PPG), Partial Product Accumulator (PPA), and Final Stage Adder (FSA) as shown in Figure 21. The PPG stage first generates partial products from the multiplicand and multiplier in parallel. The PPA stage then performs multi-operand addition for all the generated partial products and produces their sum in carry-save form. Finally, the carry-save form is converted to the corresponding binary output at FSA.
> generate multipliers

Figure 21. Architecture of a multiplier

Constant-coefficient multipliers

AMG provides constant-coefficient multipliers in the form: P=R*x, where R is an integer coefficient, and X and P are the integer input and output. The hardware algorithms for constant-coefficient multiplication are based on multi-input 1-output addition algorithms (i.e., combinations of PPAs and FSAs). There are many possible choices for the multiplier structure for a specific coefficient R. The complexity of multiplier structures significantly varies with the coefficient value R.

We consider here the use of special number representation called Signed-Weight (SW) number system, which is useful for constructing compact PPAs. At present, the combination of CSD (Canonic Signed-Digit) coefficient encoding technique with the SW-based PPAs seems to provide the practical hardware implementation of fast constant-coefficient multipliers. As a result, AMG supports such hardware algorithms for constant-coefficient multiplication, where the range of R is from -231 to 231-1. A constant-coefficient multiplier is given as a part of MACs as follow.
> generate constant-coefficient multiplications

Multiply-accumulators (MACs)

AMG provides multiply accumulators in the form: P = ∑ Xi * Yi, where Xi indicates an integer variable or constant, Yi indicates an integer variable. Figure 22 shows a n-term multiply accumulator. A multiply accumulator is generated by a combination of hardware algorithms for multipliers and constant-coefficient multipliers. All the partial products from PPGs are accumulated in carry-save form by a single PPA. The carry-save form is converted to the corresponding binary output by an FSA. Figure 23 show a simple multiply accumulators with function P = X*Y+Z, which is frequently used in DSP systems.
> generate generalized MAC
> generate simple MAC

Generalized MAC
Simple MAC
Figure 22. Generalized MAC
Figure 23. Simple MAC

Figure 24 shows how the MAC is employed in actual DSP applications. The structure (a) illustrates a typical situation, where the MAC is used to perform a multiply-add operation in an iterative fashion. On the other hand, the structure (b) shows a faster design, where two product terms are computed simultaneously in a single iteration. You can further increase the number of product terms computed in a single cycle depending on your target applications.

MAC example 1
MAC example 1
Figure 24. Application of MAC


  1. I. Koren, "Computer Arithmetic Algorithms", A K Peters, 2001.
  2. B. Parhami, "Computer Arithmetic: Algorithms and Hardware Designs", Oxford University Press, 2000.
  3. C. S. Wallace, "A suggestion for a fast multiplier", IEEE Trans. Computers, Vol. EC-13, pp. 14--17, February 1964.
  4. D. Zuras and W. H. McAllister, "Balanced delay trees and combinatorial division in VLSI", IEEE J. Solid-State Circuits, Vol. SC-21, No. 5, pp. 814--819, October 1986.
  5. Z. J. Mou and F. Jutand, " Overturned-stairs adder trees and multiplier design", IEEE Trans. Computers, Vol. C-41, No. 8, pp. 940--948, August 1992.
  6. L. Dadda, "Some schemes for parallel multipliers", Alta Frequenza, Vol. 34, No. 5, pp. 349--356, March 1965.

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